The transmission of various types of information as digital data continues to grow in importance. Quadrature amplitude modulation (QAM) and Quadrature phase shift keying (QPSK) are increasingly seeing use as an attractive vehicle to transmit digital data.
As will be discussed in detail below, the carrier recovery methods and apparatus of the present invention may be used with QAM, QPSK and a variety of other types of modulated signals. For purposes of explanation, the methods and apparatus of the present invention will be explained in the context of an exemplary QAM demodulator embodiment. QAM and known QAM carrier recovery will now be briefly discussed.
In essence, QAM relies on transmitting data as a sequence of two-dimensional complex symbols, i.e. with both in-phase and quadrature components. Each symbol, based upon the data it represents, takes on a specific pre-defined value. A set of all of the values available for transmission defines an alphabet which, when graphically plotted, typically on a two-dimensional basis, forms a constellation. The size and shape of the constellation depends upon the number of discrete values in the set and their spatial location in the constellation. The constellation frequently proposed for use in broadcasting, e.g., high definition television (HDTV) data contains, e.g., 16, 32 or 64 values (states), hence so-called 16, 32 or 64 QAM, respectively.
FIG. 1 illustrates a 16-QAM constellation. Each symbol in the constellation is denoted by an "x". In known 16 QAM the permissible nominal symbol values for both the x and y coordinates is (.+-.1, .+-.3) with the nominal squared magnitudes being approximately 2, 10 and 18. Constellation 110 ordinarily contains three rings corresponding to the squared symbol magnitudes 2, 10, 18, of which only the inner most and middle rings 113, 117, respectively, are specifically shown.
To receive broadcast QAM data, a QAM receiver essentially samples and filters a received output of a communication channel, and applies resulting filtered samples to a decoder (e.g. a Viterbi decoder), which contains one or more slicers, to yield detected symbols. The data contained in these latter symbols, if it contains compressed video information, is then appropriately decompressed to yield original source video data. To specifically accomplish QAM reception, a QAM demodulator within the receiver performs the functions of timing recovery, equalization and carrier recovery.
In QAM and QPSK carrier recovery is typically performed on a decision directed basis and in the absence of a pilot tone. Carrier recovery creates a reference carrier against which in-phase and quadrature modulated components may be determined, e.g., both in terms of frequency and phase, such that the received demodulated symbols do not rotate. It is the carrier signal that is quadrature modulated by the symbols and then transmitted to a receiver. Carrier recovery must be able to properly function in the presence of varying frequency offsets, e.g., drift or jitter that often occur between a transmitter and receiver. The input to a carrier recovery circuit is normally equalized symbols.
FIG. 2 illustrates a known carrier recovery circuit 101. As illustrated the carrier recovery circuit 101 includes a de-rotator 102, a phase detector 104, loop filter 110, phase accumulator 112, ROM 114 for storing a SINE, COSINE lookup table, and a slicer module 106. A mode select control circuit 118 is also included to control switching between acquisition and tracking modes of operation. The carrier recovery circuit 101 may be the same as, or similar to, that described in U.S. Pat. No. 5,471,508 which describes one of Applicant's earlier inventions in detail. In the illustrated embodiment, the slicer module 106 operates, in response to a control signal output by the mode select control circuit 118, in either an acquisition or tracking mode. In carrier recovery circuits which do not support distinct tracking and acquisition modes of operation the acquisition module 122 is omitted from the slicer module 106 and the mode select control circuit 118 is also omitted.
As will be discussed below, various embodiments of the present invention can be used with carrier recovery circuits which support such distinct, e.g., acquisition and tracking, modes of carrier recovery operation as well as carrier recovery circuits which support only a single, e.g., tracking, mode of operation.
In the carrier recovery circuit 101, carrier recovery is performed through the use of a digital phase-locked loop (DPLL) in which a reference carrier, on leads 165, is fabricated for use in de-rotating incoming equalized symbols. To assure that the reference carrier is accurate, i.e. this carrier properly responds in the presence of jitter in the received signal or frequency and/or phase shifts between the transmitter and receiver, and thus can be used to properly de-rotate the equalized symbols, this carrier is adjusted, in terms of both a frequency and phase, within the DPLL based on an estimate of the phase error (.phi..sub.e) that occurs between each de-rotated symbol and its corresponding ideal sliced value.
Specifically, incoming equalized symbols are applied to a first input of de-rotator 102 while quadrature outputs of a sine generator, specifically the sine, cosine table stored in read only memory (ROM) 114, are applied to a second input of the de-rotator 102. For any input to the table 114, the corresponding sine output produces the in-phase component of the reference carrier; the corresponding cosine output produces the quadrature component of this carrier. The input address to ROM 114 is an integrated phase error generated by the phase accumulator 112.
The phase error signal is first synthesized by estimating the phase error between each incoming equalized de-rotated symbol (Z.sub.REC) and its corresponding ideal sliced value therefor (Z.sub.SL). In particular, each de-rotated symbol produced by de-rotator 102 is supplied to a first input of the phase detector 104 and to the input to the slicer module 106. The phase detector 104 is implemented using a half-complex multiplier 108.
In the illustrated embodiment, slicer module 106 includes a full slicer 120 and a reduced slicer 122. The full slicer generates an output for each of the received symbols by comparing them to the full set of 16 possible ideal values (in the case of 16 QAM) and selecting the one of the 16 possible ideal values closest to the input symbol value, as the full slicer's output. The reduced slicer 122 generates ideal sliced value outputs for outer, i.e., non-inner, symbols, e.g., outer corner symbols 119.sub.1, 119.sub.2, 119.sub.3, 119.sub.4, and outputs a zero as the sliced value (Z.sub.REC) when an inner symbol is received.
The reduced slicer 122 can be implemented by first comparing the magnitude of received symbol to a preselected threshold value to determine if is an outer symbol. When the threshold is not exceed, indicating a received symbol is an inner symbol a zero is output. However, if a received symbol is determined to be an outer symbol, it is compared to a reduced set of ideal symbol values, e.g., four when only the outer four points are being used for acquisition purposes, and the closest matching value is output. In such an embodiment, during acquisition mode when the reduced complexity slicer is used, the estimated phase error will be zero for received inner symbols. In such an embodiment, the received inner symbol will have little or no effect on constellation positioning.
As discussed in U.S. Pat. No. 5,471,508 outer symbols have a longer radii and thus a larger signal to additive-plus-adaptive noise ratio than inner symbols. Theory suggests that, for this reason, outer symbols generally provide more reliable information regarding the current orientation of the constellation than inner symbols. By using only such outer symbols for phase error estimates when the ambiguity regarding phase errors are the highest, e.g., during acquisition mode, faster lock on can be achieved as compared to the case where both the less reliable phase error estimates generated from inner symbols and the more reliable phase error estimates generated from outer symbols are used for correction purposes, e.g., in the case where only a single mode of carrier recovery is supported.
A multiplexer 124, which is responsive to a mode select signal generated by the mode select control circuit 118 is used to control whether the output of the full or reduced slicer 120, 122 is supplied to the second input of the phase detector 108 at any given time. The mode select control circuit 118, which controls, via the MUX 124, switching between acquisition and tracking slicer modes of operation, may be implemented using any one of a plurality of known techniques.
The output of the phase detector 104, the estimated phase error (.phi..sub.e) between each de-rotated symbol and its corresponding sliced value, is calculated as being an imaginary part of the complex product of the equalized de-rotated symbol and the conjugate (Z.sub.sl *) of the sliced value(Z.sub.sl). That is: EQU .phi..sub.e =Im(Z.sub.REC Z.sub.SL *)=.vertline.Z.sub.REC .vertline..vertline.Z.sub.SL *.vertline.sin((.phi..sub.REC -.phi..sub.SL).about..vertline.Z.sub.REC .vertline..sup.2 .phi..sub.ae
where .phi..sub.ae is the actual phase error as opposed to the estimated phase error (.phi..sub.e); PA1 .phi..sub.REC is the phase of the received symbol; and PA1 .phi..sub.SL is the (desired) phase of the sliced symbol.
In the known system of FIG. 2, the scalar phase error (.phi..sub.e) is applied to an input of second-order loop filter 110 and, from there, to phase integrator (accumulator) 112. A resulting integrated (accumulated) phase error output by the phase accumulator 112 is applied as the input to ROM 114 which is responsible for generating the second input to the de-rotator as discussed above.
While known carrier recovery circuits such as that illustrated in FIG. 2 provide satisfactory carrier recovery under most conditions, such systems may still find it difficult and relatively time consuming to pull in extremely large frequency offsets, e.g., such as those that may be encountered where a large amount of signal jitter and/or poor signal transmission conditions exist, in a reasonable amount of time. This is because the phase detector output must have a significant biased DC component over a period of time which the second order accumulator can integrate to thereby generate an accurate frequency error signal.
Accordingly, there is a need for improved carrier recovery circuits which can achieve a frequency lock in less time than existing carrier recovery circuits, particularly where large frequency errors exit. It is desirable that any such improved carrier recovery circuits be relatively easy to implement. It is also desirable, at least in some cases, that the improved carrier recovery circuits be capable of being easily combined with existing carrier recovery circuits thereby avoiding the need to entirely redesign various existing circuits. For maximum versatility, it is also beneficial that any improved carrier recovery techniques be suitable for use with multiple modulation schemes.